Jackson M., Budruk R., Winkles J., Anderson D. PCI Express Technology 3.0

MindShare Inc. 2012. — 1057 p. — ISBN 978‐0‐9836465‐2‐5.Book Topics and Organization Topics covered in this book and chapter flow are as follows:Big Picture. Provides an architectural perspective of the PCI Express technology by comparing and contrasting it with PCI and PCI‐X buses. It also introduces features of the PCI Express architecture. An overview of configuration space concepts plus methods of packet routing are described.Transaction Layer. Includes high‐level packet (TLP) format and field definitions, along with Transaction Layer functions and responsibilities such as Quality of Service, Flow Control and Transaction Ordering.Data Link Layer. Includes description of ACK/NAK error detection and correction mechanism of the Data Link Layer. DLLP format is also described.Physical Layer. Describes Lane management functions, as well as link training and initialization, reset, electrical signaling, and logical Physical Layer responsibilities associated with Gen1, Gen2 and Gen3 PCI Express.Additional System Topics. Discusses additional system topics of PCI Express, including error detection and handling, power management, interrupt handling, Hot Plug and Power Budgeting details. Additional changes made in the PCI Express 2.1 spec not described in earlier chapters are covered here.Debugging PCI Express Traffic using LeCroy Tools
Markets & Applications of PCI Express Architecture
Implementing Intelligent Adapters and Multi‐Host Systems with PCI Express Technology
Legacy Support for Locking